1. Field of Invention
The present invention relates to a method of manufacturing a metal oxide semiconductor (MOS) device; particularly, it relates to a method of manufacturing a MOS device having a lightly doped drain (LDD) structure.
2. Description of Related Art
FIGS. 1A-1E are cross-section views showing a manufacturing process of a conventional MOS device having an LDD structure. As shown in FIG. 1A, isolation regions 12 are formed in a substrate 11 to define a device area 100. The isolation regions 12 for example are formed by local oxidation of silicon (LOCOS), and the substrate 11 for example is a P-type silicon substrate. Next, as shown in FIG. 1B, a dielectric layer 13a and a stack layer 13b of a gate structure is formed in the device area 100. Then, as shown in FIG. 1C, LDD structures 14 are formed by implantation which implants N-type impurities, in the form of accelerated ions as indicated by the dash arrow lines in the figure, to the substrate 11 masked by a photo mask, the isolation regions 12, and the stack layer 13b. And then, a spacer layer 13C is formed on the sidewall of the dielectric layer 13a and the stack layer 13b as shown in FIG. 1D. The material of the spacers 13C for example may be silicon dioxide, silicon nitride, or a combination of the above. In the following process step, as shown in FIG. 1E, source and drain 15 are formed by implantation which implants N-type impurities, in the form of accelerated ions as indicated by the dash arrow lines in the figure, to the substrate 11. The regions beneath the spacers 13c will not be implanted because they are masked by the spacers 13c. The concentration of the N-type impurities of the source and drain 15 is in the order of 1015˜1016/cm2, and the concentration of the N-type impurities of the LDD structure 14 is in the order of 1012˜1013/cm2.
The MOS device provided with the LDD structures has a gradient of N-type impurities which can reduce the electric field in the device area 100 to mitigate the hot carrier effect.
The aforementioned prior art needs two photo masks and photolithography steps, to form the LDD structures 14 and the source and drain 15 respectively. Thus, the manufacturing cost is high. Besides, due to process steps between the two photolithography steps and implantation steps, such as deposition, etching, and thermal steps, etc. for forming the spacer 13c, it is hard to control the distribution of the doped impurities of the LDD structures 14 after thermal diffusion. In this regard, U.S. Pat. No. 5,966,604 discloses a method of manufacturing a MOS device having LDD structures, which moves the process steps for forming the LDD structures 14 and the source and drain 15 before the formation of the spacers 13c. However, this reduces the thermal budget, and because the concentration of the LDD structures 14 is adjusted by counter doping P-type impurities, the behavior of the impurities in the device is more complicated and less controllable.
In both the aforementioned prior art methods, the impurities are implanted to the substrate to form a gradient profile with only two different depths, which is less preferred. Another disadvantage is that, as the technology trend requires even smaller device dimension, and even shallower depths of the LDD structure 14, the source and drain 15, the implantation steps are performed by even lower energies, and thus it becomes harder to control the depths, concentrations, etc. of the impurities. Implantation by low energy is less accurate.
In view of the foregoing, the present invention provides a method of manufacturing a MOS device having an LDD structure. This method not only saves photo masks and improves the thermal budget, but also improves the distribution gradient of the impurities to further mitigate the hot carrier effect and to improve the accuracy of low energy ion implantation.